diff options
author | Jorn Tuyls <jorn.tuyls@gmail.com> | 2025-09-22 18:15:26 +0200 |
---|---|---|
committer | GitHub <noreply@github.com> | 2025-09-22 12:15:26 -0400 |
commit | faf5f28fc26430d6f0db1cdde1e9a24a1710309d (patch) | |
tree | 64b151170332fcbfde1df44042adc7a66ec9d6b1 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
parent | fd5d7c5048501c3cf2f71ab7b1544ebe5c6816b7 (diff) | |
download | llvm-faf5f28fc26430d6f0db1cdde1e9a24a1710309d.zip llvm-faf5f28fc26430d6f0db1cdde1e9a24a1710309d.tar.gz llvm-faf5f28fc26430d6f0db1cdde1e9a24a1710309d.tar.bz2 |
[mlir][arith][transforms] Fix f4E2M1FN to f32 cast (#160121)
The signed i4 bitcast was used when setting the exponent and mantissa
and instead the sign should be omitted in the comparisons.
Without this, for example the following incorrect conversion from `-0.5`
f4 to `-3.0` f32 will happen:
| Binary | F4E2M1 | f32[23:32] | f32
| 1001 | -0.5 | ~~1 1000 000 01~~ | ~~-3.0~~
**Walkthrough:**
Bits 23 and 24 are set based on:
```
Value isHalf =
arith::CmpIOp::create(b, arith::CmpIPredicate::eq, i4BitsNoSign, c0x1);
```
Because `1001 (i4) != 1`, bit 23 and 24 are set to the leading two bits
of `1001 << 2`, which is `01`. The correct bits are `00`.
Bits 25 through 31 are set based on the i4 value being greater or equal
to 4:
```
Value useLargerExp =
arith::CmpIOp::create(b, arith::CmpIPredicate::uge, i4BitsNoSign, c0x4);
```
As `1001` is a negative i4 value, this is false and those bits are
incorrectly set to `1000 000` instead of `0111 111`.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions