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| author | Hank Chang <hank.chang@sifive.com> | 2025-09-23 09:42:58 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-23 09:42:58 +0800 |
| commit | f8e51df8e57736d27587baaa5f56e532dfc6de26 (patch) | |
| tree | 74a38198497c4daba6fde9989a90b393b57d9fe0 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 18f7e03dd60d84b5da3403f10177323df01b6f92 (diff) | |
| download | llvm-f8e51df8e57736d27587baaa5f56e532dfc6de26.zip llvm-f8e51df8e57736d27587baaa5f56e532dfc6de26.tar.gz llvm-f8e51df8e57736d27587baaa5f56e532dfc6de26.tar.bz2 | |
[TTI][ASan][RISCV] reland Move InterestingMemoryOperand to Analysis and embed in MemIntrinsicInfo #157863 (#159713)
[Previously reverted due to failures on asan-rvv-intrinsics.ll, the test
case is riscv only and it is triggered by other target]
Reland [#157863](https://github.com/llvm/llvm-project/pull/157863), and
add `; REQUIRES: riscv-registered-target` in test case to skip the
configuration that doesn't register riscv target.
Previously asan considers target intrinsics as black boxes, so asan
could not instrument accurate check. This patch make
SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so
that TTI can make targets describe their intrinsic informations to asan.
Note,
1. This patch move InterestingMemoryOperand from Transforms to Analysis.
2. Extend MemIntrinsicInfo by adding a
SmallVector<InterestingMemoryOperand> member.
3. This patch does not support RVV indexed/segment load/store.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions