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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-01-07 08:11:05 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-07 08:11:05 +0700 |
| commit | f6365a47a1ad9ab6d432f6e40d14a11419e21282 (patch) | |
| tree | 47923d791d7ccb48cdf4303e633f59438747fa45 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 7e2ed35104adbf062119c39c4293eb3bc16bc51b (diff) | |
| download | llvm-f6365a47a1ad9ab6d432f6e40d14a11419e21282.zip llvm-f6365a47a1ad9ab6d432f6e40d14a11419e21282.tar.gz llvm-f6365a47a1ad9ab6d432f6e40d14a11419e21282.tar.bz2 | |
AMDGPU: Fix assert on physreg MUBUF rsrc operand (#120815)
The stack case uses a physical register and should not ordinarily
reach here, but strange things happen at -O0. The testcase still
errors because we do not yet attempt to handle arbitrary dynamic
sized allocas yet.
Fixes: SWDEV-503538
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions