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| author | Igor Breger <igor.breger@intel.com> | 2017-09-17 11:34:17 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2017-09-17 11:34:17 +0000 |
| commit | f1d388a5c5a03696349959def898e4f23bffdbdc (patch) | |
| tree | cfe8515ded9a47bd49b6825a99c6623afc23dcd6 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | e57308ecf0fad0f4dae56e43d3c76a3a47dde981 (diff) | |
| download | llvm-f1d388a5c5a03696349959def898e4f23bffdbdc.zip llvm-f1d388a5c5a03696349959def898e4f23bffdbdc.tar.gz llvm-f1d388a5c5a03696349959def898e4f23bffdbdc.tar.bz2 | |
[GlobalISel][X86] Legalize i1 G_ADD/G_SUB/G_MUL/G_XOR/G_OR/G_AND instructions.
llvm-svn: 313483
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions