diff options
| author | Sergei Barannikov <barannikov88@gmail.com> | 2023-05-24 07:12:53 +0300 |
|---|---|---|
| committer | Sergei Barannikov <barannikov88@gmail.com> | 2023-05-25 08:53:15 +0300 |
| commit | ee1d5f637286bda762de76dfc33143abd52c5460 (patch) | |
| tree | 7abb9f0e074a557204b8ceecde79a0190f2112a3 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 25174976e19b2ef916bb94f4613662646c95cd46 (diff) | |
| download | llvm-ee1d5f637286bda762de76dfc33143abd52c5460.zip llvm-ee1d5f637286bda762de76dfc33143abd52c5460.tar.gz llvm-ee1d5f637286bda762de76dfc33143abd52c5460.tar.bz2 | |
[MC] Check if register is non-null before calling isSubRegisterEq (NFCI)
D151036 adds an assertions that prohibits iterating over sub- and
super-registers of a null register. This is already the case when
iterating over register units of a null register, and worked by
accident for sub- and super-registers.
Reviewed By: Amir
Differential Revision: https://reviews.llvm.org/D151285
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions