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| author | MessyHack <messyhack@gmail.com> | 2024-03-13 14:22:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-13 16:22:23 -0500 |
| commit | ea848d0a6d5c17af3eb1a4e39dc712606ac684f6 (patch) | |
| tree | 3c8894755d53d9f5bc5142bddbdfcf6e8b85e9aa /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | b49d741c0c3bb21b40c925b4c1a717470181eb8d (diff) | |
| download | llvm-ea848d0a6d5c17af3eb1a4e39dc712606ac684f6.zip llvm-ea848d0a6d5c17af3eb1a4e39dc712606ac684f6.tar.gz llvm-ea848d0a6d5c17af3eb1a4e39dc712606ac684f6.tar.bz2 | |
[OpenMP] Sort topology after adding processor group layer. (#83943)
Various behavior around creating affinity masks and detecting uniform
topology depends on the topology being sorted.
resort topology after adding processor group layer to ensure that the
updated topology reflects the newly added processor group info.
Observed that the topology was not sorted correctly on high core count
AMD Epyc Genoa (2 sockets, 96 cores, 2 threads) using NUMA (NPS 2+).
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions