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| author | jjasmine <jjasmine@igalia.com> | 2025-07-01 15:27:37 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-01 15:27:37 -0700 |
| commit | e9c9f8f3748a1666dfd099da7990ebe4523778bf (patch) | |
| tree | c86bc678997c524bc45ba7b1ebb03453d42bec9d /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 4a8c1f7d127af06642068da56e29178704caf54d (diff) | |
| download | llvm-e9c9f8f3748a1666dfd099da7990ebe4523778bf.zip llvm-e9c9f8f3748a1666dfd099da7990ebe4523778bf.tar.gz llvm-e9c9f8f3748a1666dfd099da7990ebe4523778bf.tar.bz2 | |
[WebAssembly] Fold any/alltrue (setcc x, 0, eq/ne) to [not] any/alltrue x (#144741)
Fixes https://github.com/llvm/llvm-project/issues/50142, a miss of
further vectorization, where we can only achieve zext (xor (any_true),
-1).
Now in test case simd-setcc-reductions, it's converted to all_true.
Also fixes https://github.com/llvm/llvm-project/issues/145177, which is
all_true (setcc x, 0, eq) -> not any_true
any_true (setcc x, 0, ne) -> any_true
all_true (setcc x, 0, ne) -> all_true
---------
Co-authored-by: badumbatish <--show-origin>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions