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| author | Oliver Stannard <oliver.stannard@arm.com> | 2025-01-13 09:55:08 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-13 09:55:08 +0000 |
| commit | e2a071ece58790f8dd4886e998033cab82e906fb (patch) | |
| tree | b14c8cc965f4c308125ba8e7e4f28e09c3f858ed /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | d03f35f9b6d031d6a9375d90ccf7cc285f8e4b79 (diff) | |
| download | llvm-e2a071ece58790f8dd4886e998033cab82e906fb.zip llvm-e2a071ece58790f8dd4886e998033cab82e906fb.tar.gz llvm-e2a071ece58790f8dd4886e998033cab82e906fb.tar.bz2 | |
[MachineCP] Correctly handle register masks and sub-registers (#122472)
When passing an instruction with a register mask, the machine copy
propagation pass was dropping the information about some copy
instructions which define a register which is preserved by the mask,
because that register overlaps a register which is partially clobbered
by it. This resulted in a miscompilation for AArch64, because this
caused a live copy to be considered dead.
The fix is to clobber register masks by finding the set of reg units
which is preserved by the mask, and clobbering all units not in that
set.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions