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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-11-21 12:02:18 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-11-21 12:02:18 +0000 |
| commit | e1490afa4c9162d08f4fc550165470d781a5ffdc (patch) | |
| tree | 84144b8ca17e99df86d26a01e60bd641b1f7b234 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9caefe364af0e60e31d30a0fd45ad1b5616283c0 (diff) | |
| download | llvm-e1490afa4c9162d08f4fc550165470d781a5ffdc.zip llvm-e1490afa4c9162d08f4fc550165470d781a5ffdc.tar.gz llvm-e1490afa4c9162d08f4fc550165470d781a5ffdc.tar.bz2 | |
[X86][XOP] Add missing scheduler classes to XOP instructions
All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables.
llvm-svn: 318758
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions