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| author | Craig Topper <craig.topper@intel.com> | 2017-12-07 08:04:34 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-07 08:04:34 +0000 |
| commit | dfecd45f371584b80d050d29955324ba37c6311f (patch) | |
| tree | 944f68fc22832f04e176543942a4cafb8328e96f /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 26ed8d1263d3762f00095a3ff3d7f13887dd2728 (diff) | |
| download | llvm-dfecd45f371584b80d050d29955324ba37c6311f.zip llvm-dfecd45f371584b80d050d29955324ba37c6311f.tar.gz llvm-dfecd45f371584b80d050d29955324ba37c6311f.tar.bz2 | |
[SelectionDAG] In SplitVecOp_EXTRACT_VECTOR_ELT, simplify the code that makes the type byte addressable.
We can just extend the original vector to vXi1 and trust that the legalization process will revisit it.
llvm-svn: 320013
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions