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| author | David Green <david.green@arm.com> | 2024-11-29 04:01:03 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-29 04:01:03 +0000 |
| commit | d714b221c77203107284544b8f5543bd4c35ccc9 (patch) | |
| tree | 7a0ccdeeda4840bc8c40c5f6931a8745fc90fe7a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | dab9fa2d7f3b3092d4ab0c815868ec68a968a31a (diff) | |
| download | llvm-d714b221c77203107284544b8f5543bd4c35ccc9.zip llvm-d714b221c77203107284544b8f5543bd4c35ccc9.tar.gz llvm-d714b221c77203107284544b8f5543bd4c35ccc9.tar.bz2 | |
[AArch64] Guard against getRegisterBitWidth returning zero in vector instr cost. (#117749)
If the getRegisterBitWidth is zero (such as in sme streaming functions),
then we could hit a crash from using % RegWidth.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions