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| author | Ting Wang <Ting.Wang.SH@ibm.com> | 2023-02-21 06:14:47 -0500 |
|---|---|---|
| committer | Ting Wang <Ting.Wang.SH@ibm.com> | 2023-02-21 06:14:47 -0500 |
| commit | d567e06946b70136d344df3d8601c5e02cb596e1 (patch) | |
| tree | 7a30aca9c0c685b0a717a4156bee5916109764b2 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9f5ae702edbca5e9880a9847d9e869aa516482d8 (diff) | |
| download | llvm-d567e06946b70136d344df3d8601c5e02cb596e1.zip llvm-d567e06946b70136d344df3d8601c5e02cb596e1.tar.gz llvm-d567e06946b70136d344df3d8601c5e02cb596e1.tar.bz2 | |
[PowerPC][NFC] refactor eligible check for tail call optimization
The check logic for TCO is scattered in two functions:
IsEligibleForTailCallOptimization_64SVR4() IsEligibleForTailCallOptimization(),
and serves instruction selection phase only at this moment.
This patch aims to refactor existing logic to export an API for TCO
eligible query before instruction selection phase.
Reviewed By: shchenz, nemanjai
Differential Revision: https://reviews.llvm.org/D141673
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions