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| author | Craig Topper <craig.topper@sifive.com> | 2025-01-27 20:54:07 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2025-01-27 22:10:51 -0800 |
| commit | d4af658323c6e2492ca1224930488c390a08c720 (patch) | |
| tree | f6646243ce5e5f036e804d6337fae215da0ff518 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | f10441ad003236ef3b9e5415a571d2be0c0ce5ce (diff) | |
| download | llvm-d4af658323c6e2492ca1224930488c390a08c720.zip llvm-d4af658323c6e2492ca1224930488c390a08c720.tar.gz llvm-d4af658323c6e2492ca1224930488c390a08c720.tar.bz2 | |
[RISCV] Support multiple memory operands in expandRV32ZdinxStore.
TailMerge can create stores with multiple memory operands. We
need to split all of them instead of assuming there is only one.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions