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| author | Jerry-Ge <jerry.ge@arm.com> | 2025-02-21 08:38:45 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-21 08:38:45 -0800 |
| commit | d12a4d45dd43410b50aa0e86015f5224dac5cf92 (patch) | |
| tree | cca35cb618bb01d965ed4242aa340d6d0ea74910 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | aa6d3ff80d93b2f4635ace198e42e66a42184315 (diff) | |
| download | llvm-d12a4d45dd43410b50aa0e86015f5224dac5cf92.zip llvm-d12a4d45dd43410b50aa0e86015f5224dac5cf92.tar.gz llvm-d12a4d45dd43410b50aa0e86015f5224dac5cf92.tar.bz2 | |
[mlir][tosa] Remove section numbers in operator tablegen (#128048)
The section numbers don't currently match what is in the v1.0
spec(https://www.mlplatform.org/tosa/tosa_spec.html) It can be a burden
to remember to update these, and they didn't seem to have much use, so
proposing to remove these comments.
Signed-off-by: Luke Hutton <luke.hutton@arm.com>
Co-authored-by: Luke Hutton <luke.hutton@arm.com>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions