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| author | Yashwant Singh <Yashwant.Singh@amd.com> | 2023-02-08 11:41:51 +0530 |
|---|---|---|
| committer | Yashwant Singh <Yashwant.Singh@amd.com> | 2023-02-08 11:45:48 +0530 |
| commit | cde2f330b36fc36760329be1d3c52e92da400663 (patch) | |
| tree | d1b18b037430437e54b333999dc639a6dc9ebe2a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 1cf344d9465a924536f548e87386977ea5cf908c (diff) | |
| download | llvm-cde2f330b36fc36760329be1d3c52e92da400663.zip llvm-cde2f330b36fc36760329be1d3c52e92da400663.tar.gz llvm-cde2f330b36fc36760329be1d3c52e92da400663.tar.bz2 | |
[AMDGPU] Introduce never uniform bit field in tablegen
IsNeverUniform can be set to 1 to mark instructions which are
inherently never-uniform/divergent. Enabling this bit in
Writelane instruction for now. To be extended to all required
instructions.
Reviewed By: arsenm, sameerds, #amdgpu
Differential Revision: https://reviews.llvm.org/D143154
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions