diff options
| author | Kishan Parmar <kparmar2101@gmail.com> | 2023-06-21 10:16:43 +0000 |
|---|---|---|
| committer | David Spickett <david.spickett@linaro.org> | 2023-06-21 10:24:40 +0000 |
| commit | c42f0a6e6476971974cb3f52c1138dbd8f9cca1f (patch) | |
| tree | c1d6ca23179e3c87dcb6f02ceb0f44863e2438d7 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 64df75fb26e55c097e79df6770a99d4b1ad09716 (diff) | |
| download | llvm-c42f0a6e6476971974cb3f52c1138dbd8f9cca1f.zip llvm-c42f0a6e6476971974cb3f52c1138dbd8f9cca1f.tar.gz llvm-c42f0a6e6476971974cb3f52c1138dbd8f9cca1f.tar.bz2 | |
PowerPC/SPE: Add phony registers for high halves of SPE SuperRegs
The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31)
as artificial regs, similar to how X86 has done it.
And emit store /reload instructions for the required halves.
PR : https://github.com/llvm/llvm-project/issues/57307
Reviewed By: jhibbits
Differential Revision: https://reviews.llvm.org/D152437
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions