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| author | Virginia Cangelosi <virginia.cangelosi@arm.com> | 2025-04-28 10:00:07 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-28 10:00:07 +0100 |
| commit | be7cf63b4a402ebc5b1dacc6579a693c92e1328e (patch) | |
| tree | f5bc57ecffc5736dd15ed912e275e351b3e38ac6 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 92bfbbc4e5f4c7c6a7b677b1da9765b2507a98ce (diff) | |
| download | llvm-be7cf63b4a402ebc5b1dacc6579a693c92e1328e.zip llvm-be7cf63b4a402ebc5b1dacc6579a693c92e1328e.tar.gz llvm-be7cf63b4a402ebc5b1dacc6579a693c92e1328e.tar.bz2 | |
[AArch64] Add FPCR register usages to mop4 instructions (#135641)
Ensure all floating mop4 instructions implicitly use FPCR
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions