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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2025-01-12 15:59:05 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-12 15:59:05 +0000 |
| commit | be6c752e157638849f1f59f7e2b7ecbe11a022fe (patch) | |
| tree | 5d6e92ad2f0f1b462f9692af20d259e3b479a8b3 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 4f7dc1b55ae5b8ed1a36dd941ef4f9920bfdac8d (diff) | |
| download | llvm-be6c752e157638849f1f59f7e2b7ecbe11a022fe.zip llvm-be6c752e157638849f1f59f7e2b7ecbe11a022fe.tar.gz llvm-be6c752e157638849f1f59f7e2b7ecbe11a022fe.tar.bz2 | |
[X86] X86FixupVectorConstantsPass - use VPMOVSX/ZX extensions for PS/PD domain moves (#122601)
For targets with free domain moves, or AVX512 support, allow the use of VPMOVSX/ZX extension loads to reduce the load sizes.
I've limited this to extension to i32/i64 types as we're mostly interested in shuffle mask loading here, but we could include i16 types as well just as easily.
Inspired by a regression on #122485
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions