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authorDavid Green <david.green@arm.com>2024-11-08 16:18:22 +0000
committerGitHub <noreply@github.com>2024-11-08 16:18:22 +0000
commit92a9bcc84d435ce28d59e7b07e2fb83a7f6bca63 (patch)
tree6810dd15db4e97ae8ad05a0ef4f05ede49c638ed /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
parent3356eb3b15f391b9b4f62b0157fede16bd8cd5b3 (diff)
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[AArch64] Add tablegen patterns for fmla index with extract 0. (#114976)
We have tablegen patterns to produce an indexed `fmla s0, s1, v2.s[2]` from `fma extract(Rn, lane), Rm, Ra -> fmla` But for the case of lane==0, we want to prefer the simple `fmadd s0, s1, s2`. So we have patterns for `fma extract(Rn, 0), Rm, Ra -> fmadd` The problem arises when we have two extracts, as tablegen starts to prefer the second pattern, as it looks more specialized. This patch adds additional patterns to catch this case: `fma extract(Rn, index), extract(Rm, 0), Ra -> fmla` To make sure the simpler fmadd keeps being selected when both lanes are extracted from lane 0 we need to add patterns for that case too: `fma extract(Rn, 0), extract(Rm, 0), Ra -> fmadd`
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
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