diff options
| author | Shengchen Kan <shengchen.kan@intel.com> | 2023-05-07 22:20:36 +0800 |
|---|---|---|
| committer | Shengchen Kan <shengchen.kan@intel.com> | 2023-05-08 13:27:36 +0800 |
| commit | 8d657c461a5aa43e882071b3b5e0496961aa44a1 (patch) | |
| tree | 7234e4eb111fc38eab223ac838eabf905aee044b /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9c1d5e4ae3498d22287c6f36f7f029bab6cd5d81 (diff) | |
| download | llvm-8d657c461a5aa43e882071b3b5e0496961aa44a1.zip llvm-8d657c461a5aa43e882071b3b5e0496961aa44a1.tar.gz llvm-8d657c461a5aa43e882071b3b5e0496961aa44a1.tar.bz2 | |
[X86][AsmParser] Refactor code in AsmParser
1. Share code `optimizeInstFromVEX3ToVEX2` with MCInstLower
2. Move the code of optimization for shift/rotate to a separate file
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D150068
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions