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authorDavid Spickett <david.spickett@linaro.org>2023-06-05 17:02:09 +0000
committerDavid Spickett <david.spickett@linaro.org>2023-06-21 09:28:48 +0000
commit8b73a2e8219127b707280b689edb20753849bd4c (patch)
treed758c8ed20299044c5ea7def2018ec7153043251 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
parent92af1183c3f1a7621bceab29461cbc80c5ca3e26 (diff)
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[LLDB] Add table formatting for register fields
This will be used by the "register info" command to show the layout of register contents. For example if we have these fields coming in from XML: ``` <field name="D" start="0" end="7"/> <field name="C" start="8" end="15"/> <field name="B" start="16" end="23"/> <field name="A" start="24" end="31"/> ``` We get: ``` | 31-24 | 23-16 | 15-8 | 7-0 | |-------|-------|------|-----| | A | B | C | D | ``` Note that this is only the layout, not the values. For values, use "register read". The tables' columns are center padded (left bias if there's an odd padding) and will wrap if the terminal width is too low. ``` | 31-24 | 23-16 | |-------|-------| | A | B | | 15-8 | 7-0 | |------|-----| | C | D | ``` This means we match the horizontal format seen in many architecture manuals but don't spam the user with lots of misaligned text when the output gets very long. Reviewed By: jasonmolenda Differential Revision: https://reviews.llvm.org/D152917
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