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| author | Akshay Deodhar <adeodhar@nvidia.com> | 2025-01-22 19:37:11 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-22 19:37:11 -0800 |
| commit | 892a804d93d44ddfd7cd351852fe6aef32d4dcd0 (patch) | |
| tree | cf7206cee01402ffde968ef972d82756857a317a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 652ff20140d79544db4dfa21314fc62c3c9182e5 (diff) | |
| download | llvm-892a804d93d44ddfd7cd351852fe6aef32d4dcd0.zip llvm-892a804d93d44ddfd7cd351852fe6aef32d4dcd0.tar.gz llvm-892a804d93d44ddfd7cd351852fe6aef32d4dcd0.tar.bz2 | |
[NVPTX] Stop using 16-bit CAS instructions from PTX (#120220)
Increases minimum CAS size from 16 bit to 32 bit, for better SASS
codegen.
When atomics are emulated using atom.cas.b16, the SASS generated
includes 2 (nested) emulation loops. When emulated using an atom.cas.b32
loop, the SASS too has a single emulation loop. Using 32 bit CAS thus
results in better codegen.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions