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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 12:45:05 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 12:45:05 +0000 |
| commit | 87a54d611042449aff1c8f6ceee417af85dee193 (patch) | |
| tree | 849c061a2c3f06b8df0624632425185aa430a61d /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 1cf9c54e5c74e6e8a5d4cb152b105ab6c5964739 (diff) | |
| download | llvm-87a54d611042449aff1c8f6ceee417af85dee193.zip llvm-87a54d611042449aff1c8f6ceee417af85dee193.tar.gz llvm-87a54d611042449aff1c8f6ceee417af85dee193.tar.bz2 | |
[RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot
Simply checking for register class equality will break once additional
register classes are added (as is done for the RVC instruction set extension).
llvm-svn: 320036
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions