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| author | Jianhui Li <jian.hui.li@intel.com> | 2025-06-17 17:48:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-17 19:48:09 -0500 |
| commit | 86a09f36154fbd264f61ea6462c8cf48b1ff2eb0 (patch) | |
| tree | ed6e4ae16f201e3e743e567dc79900d7995c663a /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 4e090b6e84e33e2a442e3951253ca570f8f842f8 (diff) | |
| download | llvm-86a09f36154fbd264f61ea6462c8cf48b1ff2eb0.zip llvm-86a09f36154fbd264f61ea6462c8cf48b1ff2eb0.tar.gz llvm-86a09f36154fbd264f61ea6462c8cf48b1ff2eb0.tar.bz2 | |
[MLIR][XeGPU] Clean up xegpu op tests (#144592)
Test cleanup:
1) separate layout.mlir from ops.mlir for layout related test
2) remove lane layout for ops working at work item scope.
3) remove redundant test in create_tdesc/update_tdesc/prefetch.
4) remove "test_" from all test function name.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions