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| author | Alex MacLean <amaclean@nvidia.com> | 2025-03-28 14:13:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-28 14:13:36 -0700 |
| commit | 812e02a74c0afb8bce8bf7ac7cc606ace188e30d (patch) | |
| tree | 593b0e838d7b9997b7f45bf667aefb6283b53126 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | c0952a931c7d556ca9f0073d86d591a37eb60477 (diff) | |
| download | llvm-812e02a74c0afb8bce8bf7ac7cc606ace188e30d.zip llvm-812e02a74c0afb8bce8bf7ac7cc606ace188e30d.tar.gz llvm-812e02a74c0afb8bce8bf7ac7cc606ace188e30d.tar.bz2 | |
[NVPTX] Use fast-math flags when lowering sin, cos, frem (#133121)
Update the lowering rules for sin, cos, and frem to respect the
instruction-level flags in addition to the global and function-level
options. For sin and cos, the TableGen lowering has been updated to
check the `afn` flag on the node. The lowering for frem has been pulled
to custom instruction legalization in order to allow for DAG Combiner
optimizations to operate over the expanded instructions.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions