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| author | Alex MacLean <amaclean@nvidia.com> | 2025-05-21 08:14:15 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-21 08:14:15 -0700 |
| commit | 735209c0688b10a66c24750422b35d8c2ad01bb5 (patch) | |
| tree | 9643b883fab1860533019fd15f779597eb50a2b4 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | a28d753e9645f62bff4d65c5ddce17e11e8fd078 (diff) | |
| download | llvm-735209c0688b10a66c24750422b35d8c2ad01bb5.zip llvm-735209c0688b10a66c24750422b35d8c2ad01bb5.tar.gz llvm-735209c0688b10a66c24750422b35d8c2ad01bb5.tar.bz2 | |
[NVPTX] Unify and extend barrier{.cta} intrinsic support (#140615)
Our current intrinsic support for barrier intrinsics is confusing and
incomplete, with multiple intrinsics mapping to the same instruction and
intrinsic names not clearly conveying intrinsic semantics. Further, we
lack support for some variants. This change unifies the IR
representation to a single consistently named set of intrinsics.
- llvm.nvvm.barrier.cta.sync.aligned.all(i32)
- llvm.nvvm.barrier.cta.sync.aligned(i32, i32)
- llvm.nvvm.barrier.cta.arrive.aligned(i32, i32)
- llvm.nvvm.barrier.cta.sync.all(i32)
- llvm.nvvm.barrier.cta.sync(i32, i32)
- llvm.nvvm.barrier.cta.arrive(i32, i32)
The following Auto-Upgrade rules are used to maintain compatibility with
IR using the legacy intrinsics:
* llvm.nvvm.barrier0 --> llvm.nvvm.barrier.cta.sync.aligned.all(0)
* llvm.nvvm.barrier.n --> llvm.nvvm.barrier.cta.sync.aligned.all(x)
* llvm.nvvm.bar.sync --> llvm.nvvm.barrier.cta.sync.aligned.all(x)
* llvm.nvvm.barrier --> llvm.nvvm.barrier.cta.sync.aligned(x, y)
* llvm.nvvm.barrier.sync --> llvm.nvvm.barrier.cta.sync.all(x)
* llvm.nvvm.barrier.sync.cnt --> llvm.nvvm.barrier.cta.sync(x, y)
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions