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| author | Csanád Hajdú <csanad.hajdu@arm.com> | 2025-02-21 18:01:38 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-21 09:01:38 -0800 |
| commit | 6e457c20016ae1ed7249dd28ce4b3c7993a91275 (patch) | |
| tree | 18dad4e378e9e837cc2565f6ceca70dcc878c0ad /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | cf50936b23ac25c786d66be6d7b9277398cddde5 (diff) | |
| download | llvm-6e457c20016ae1ed7249dd28ce4b3c7993a91275.zip llvm-6e457c20016ae1ed7249dd28ce4b3c7993a91275.tar.gz llvm-6e457c20016ae1ed7249dd28ce4b3c7993a91275.tar.bz2 | |
[LLD][ELF][AArch64] Add support for SHF_AARCH64_PURECODE ELF section flag (3/3) (#125689)
Add support for the new SHF_AARCH64_PURECODE ELF section flag:
https://github.com/ARM-software/abi-aa/pull/304
The general implementation follows the existing one for ARM targets. The
output section only has the `SHF_AARCH64_PURECODE` flag set if all input
sections have it set.
Related PRs:
* LLVM: https://github.com/llvm/llvm-project/pull/125687
* Clang: https://github.com/llvm/llvm-project/pull/125688
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions