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| author | Ramkumar Ramachandra <ramkumar.ramachandra@codasip.com> | 2025-01-12 15:19:29 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-12 15:19:29 +0000 |
| commit | 66badf224ade6e78d5da005f6a9819092fd8767b (patch) | |
| tree | 1dbc533b6906821d87d37dbb0e39cca892824947 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 26b4a0ac7ed3f04f10bd1c043e2cf9c52da7fc47 (diff) | |
| download | llvm-66badf224ade6e78d5da005f6a9819092fd8767b.zip llvm-66badf224ade6e78d5da005f6a9819092fd8767b.tar.gz llvm-66badf224ade6e78d5da005f6a9819092fd8767b.tar.bz2 | |
VT: teach a special-case optz about samesign (#122590)
There is a narrow special-case in isImpliedCondICmps that can benefit
from being taught about samesign. Since it costs us nothing to implement
it, teach it about samesign, for completeness. This patch marks the
completion of the effort to teach ValueTracking about samesign.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions