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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-03-22 05:33:27 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-21 17:03:27 -0700 |
| commit | 6419905f53d4dbdb9d49358115ccba873f674dd4 (patch) | |
| tree | 22a12f012421c5971b00176ea8013ecc99d5fb51 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 718838d128f201279c489f0a2959fec4f47a42be (diff) | |
| download | llvm-6419905f53d4dbdb9d49358115ccba873f674dd4.zip llvm-6419905f53d4dbdb9d49358115ccba873f674dd4.tar.gz llvm-6419905f53d4dbdb9d49358115ccba873f674dd4.tar.bz2 | |
[RISCV] Correct qc.e.li instruction definition (#132380)
The instruction has no tied operands. It was incorrectly using
QCIRVInstEAI which has a tied operand for the destination register.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions