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| author | Craig Topper <craig.topper@sifive.com> | 2025-08-22 11:33:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-22 11:33:27 -0700 |
| commit | 3c609f3984b1a9d9f4e24d61f5d0f65df830498d (patch) | |
| tree | 101dd364c0efdfa6eb91188bfb6179d427a29857 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | bcc27dcc228b6335161fa8e4b21b82adb2452c5e (diff) | |
| download | llvm-3c609f3984b1a9d9f4e24d61f5d0f65df830498d.zip llvm-3c609f3984b1a9d9f4e24d61f5d0f65df830498d.tar.gz llvm-3c609f3984b1a9d9f4e24d61f5d0f65df830498d.tar.bz2 | |
[RISCV] Merge int_riscv_masked_atomicrmw_*_i32/i64 intrinsics using llvm_anyint_ty. (#154845)
I think having separate intrinsics for RV32 and RV64 is making
some things more complicated than using type overloading.
This reduces the number of isel patterns in the .td file. They're
still expanded my HwMode so it doesn't reduce the binary size.
getIntrinsicForMaskedAtomicRMWBinOp no longer needs to look at XLen.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions