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| author | zhongyunde <zhongyunde@huawei.com> | 2023-02-07 10:59:04 +0800 |
|---|---|---|
| committer | zhongyunde <zhongyunde@huawei.com> | 2023-02-07 11:03:50 +0800 |
| commit | 39af4659f24026fd3c667ce50a9e798485e1ae98 (patch) | |
| tree | f3e635c014dfb8c029a779ee39fd73f1e6ff9257 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 3df16e6f6e4d933f3839003e29b8a4b70e4c7ec8 (diff) | |
| download | llvm-39af4659f24026fd3c667ce50a9e798485e1ae98.zip llvm-39af4659f24026fd3c667ce50a9e798485e1ae98.tar.gz llvm-39af4659f24026fd3c667ce50a9e798485e1ae98.tar.bz2 | |
[AArch64][SVE] Replace destructive operand of vector zeros with a bundled MOVPRFX instruction
Replace unary instructions where the destructive operand is a vector of zeros
with a bundled MOVPRFX instruction, e.g:
Transform:
%X0 = DUP_ZI_S 0, 0
%X0 = FLOGB_ZPmZ_S X0, P0, X2
into:
X0 = MOVPRFX P0/z, X1 // doesn't introduce any fake register dependencies compare to X0 = MOVPRFX P0/z, X0
X0 = FLOGB_ZPmZ_S X0, P0, X2
NOTE: This patch add a @earlyclobber constraint to PredOneOpPassthruPseudo to ensure
safe register allocation for movprfx usage.
Depends on D105889
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D138888
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions