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| author | CHANDRA GHALE <chandra.nitdgp@gmail.com> | 2025-01-12 23:38:00 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-12 23:38:00 +0530 |
| commit | 1d2eea962ac9724350f025f4c70808d42a435289 (patch) | |
| tree | dae1018508647f80c80073f5f712632bc376971c /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 9dee7c44491635ec9037b90050bcdbd3d5291e38 (diff) | |
| download | llvm-1d2eea962ac9724350f025f4c70808d42a435289.zip llvm-1d2eea962ac9724350f025f4c70808d42a435289.tar.gz llvm-1d2eea962ac9724350f025f4c70808d42a435289.tar.bz2 | |
[OpenMP] codegen support for masked combined construct masked taskloop simd (#121916)
Added codegen support for combined masked constructs `masked taskloop
simd`.
Added implementation for `EmitOMPMaskedTaskLoopSimdDirective`.
Co-authored-by: Chandra Ghale <ghale@pe31.hpc.amslabs.hpecorp.net>
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions