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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-01-23 09:06:26 +0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-01-23 09:06:26 +0700 |
| commit | 15c2d4baf17292b4966d335846b30c50063f0265 (patch) | |
| tree | e231ddce2a77a4b5ff2c98341fcc934db4f081ee /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | ba70368f1380f8d22494fc8c100d2ab894a3cf94 (diff) | |
| download | llvm-15c2d4baf17292b4966d335846b30c50063f0265.zip llvm-15c2d4baf17292b4966d335846b30c50063f0265.tar.gz llvm-15c2d4baf17292b4966d335846b30c50063f0265.tar.bz2 | |
PeepholeOpt: Remove check for subreg index on a def operand (#123943)
This is looking at operand 0 of a REG_SEQUENCE, which can never
have a subregister index.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions