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| author | CarolineConcatto <caroline.concatto@arm.com> | 2024-01-10 17:12:14 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-10 17:12:14 +0000 |
| commit | 14e7dac92a32f900a66cb868be89c964b687a825 (patch) | |
| tree | 41ee6968da3f22038a2c466cb52c14e6a4dcb7a5 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | d7ac4123333a5bc042b2eb9e17df8f723f6b56d9 (diff) | |
| download | llvm-14e7dac92a32f900a66cb868be89c964b687a825.zip llvm-14e7dac92a32f900a66cb868be89c964b687a825.tar.gz llvm-14e7dac92a32f900a66cb868be89c964b687a825.tar.bz2 | |
[Clang][LLVM][AArch64]SVE2.1 update the intrinsics according to acle[1] (#76844)
This patch changes the following intrinsic
```svst1uwq[_{d}] replaced by svst1wq[_{d}]
svst1uwq_vnum[_{d}] replaced by svst1wq_vnum[_{d}]
svst1udq[_{d}] replaced by svst1dq[_{d}]
svst1udq_vnum[_{d}] replaced by svst1dq_vnum[_{d}]
```
Drops 'u' from the quadword stores because it is simply truncating the
quadwords to 32 bits
```
svextq_lane[_{d}] replaced by svextq[_{d}]
```
EXTQ follows the previous defined EXT intrinsics
```
svdot[_{d}_{2}_{3}] replaced by svdot[_{d}_{2}]
```
Introduced with the latest SME2 ACLE change
[1]https://github.com/ARM-software/acle/pull/257
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions