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| author | Brox Chen <guochen2@amd.com> | 2025-03-26 18:38:20 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-26 18:38:20 -0400 |
| commit | 06411399fb6f29277cfb3601f8c9603778f20224 (patch) | |
| tree | 9ef91346d1234df4ecb1c020fa4494d19dbf1d63 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 6075275e68bd2362095af76b1acb49c2ac9610a4 (diff) | |
| download | llvm-06411399fb6f29277cfb3601f8c9603778f20224.zip llvm-06411399fb6f29277cfb3601f8c9603778f20224.tar.gz llvm-06411399fb6f29277cfb3601f8c9603778f20224.tar.bz2 | |
[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)
Added a srl pattern for true16 flow. Changing right shift 16bit to a
reg_sequence
`srl vgpr32, 16 -> reg_sequence (vgpr32.hi16, 0)`
and finally it's lowered to two COPY
`vdst.lo16 = COPY vsrc.hi16`
`vdst.hi16 = COPY 0`
The benefits of this transform is allowing the following pass to
optimize out these copy.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions