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author | Eugene Zelenko <eugene.zelenko@gmail.com> | 2017-07-26 23:20:35 +0000 |
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committer | Eugene Zelenko <eugene.zelenko@gmail.com> | 2017-07-26 23:20:35 +0000 |
commit | e4fc6ee790009a1486af2ec1c0ee4f55d1ef6a26 (patch) | |
tree | 671c1eb69f6a406a0a30ede46e652989f166f8b6 /llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | |
parent | 08e38d6b3d89bd04a41c1a0518ef8e7217a72b38 (diff) | |
download | llvm-e4fc6ee790009a1486af2ec1c0ee4f55d1ef6a26.zip llvm-e4fc6ee790009a1486af2ec1c0ee4f55d1ef6a26.tar.gz llvm-e4fc6ee790009a1486af2ec1c0ee4f55d1ef6a26.tar.bz2 |
[Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 309230
Diffstat (limited to 'llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 586220d..a804857 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -1,4 +1,4 @@ -//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// +//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===// // // The LLVM Compiler Infrastructure // @@ -24,6 +24,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Endian.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" @@ -35,7 +36,7 @@ using namespace llvm; using namespace Hexagon; -typedef MCDisassembler::DecodeStatus DecodeStatus; +using DecodeStatus = MCDisassembler::DecodeStatus; namespace { @@ -60,37 +61,38 @@ public: void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; }; -namespace { - uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, - int64_t Value) { - MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( - MCB, HexagonMCInstrInfo::bundleSize(MCB)); - if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) - return Value; - unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); - uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; - int64_t Bits; - bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); - assert(Success); (void)Success; - uint32_t Upper26 = static_cast<uint32_t>(Bits); - uint32_t Operand = Upper26 | Lower6; - return Operand; - } - HexagonDisassembler const &disassembler(void const *Decoder) { - return *static_cast<HexagonDisassembler const *>(Decoder); - } - template <size_t T> - void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { - HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = - fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, - SignExtend64<T>(tmp)); - int64_t Extended = SignExtend64<32>(FullValue); - HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); - } -} } // end anonymous namespace +static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, + int64_t Value) { + MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( + MCB, HexagonMCInstrInfo::bundleSize(MCB)); + if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) + return Value; + unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); + uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; + int64_t Bits; + bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); + assert(Success); (void)Success; + uint32_t Upper26 = static_cast<uint32_t>(Bits); + uint32_t Operand = Upper26 | Lower6; + return Operand; +} + +static HexagonDisassembler const &disassembler(void const *Decoder) { + return *static_cast<HexagonDisassembler const *>(Decoder); +} + +template <size_t T> +static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { + HexagonDisassembler const &Disassembler = disassembler(Decoder); + int64_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, + SignExtend64<T>(tmp)); + int64_t Extended = SignExtend64<32>(FullValue); + HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); +} + // Forward declare these because the auto-generated code will reference them. // Definitions are further down. @@ -198,8 +200,7 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return MCDisassembler::Success; } -namespace { -void adjustDuplex(MCInst &MI, MCContext &Context) { +static void adjustDuplex(MCInst &MI, MCContext &Context) { switch (MI.getOpcode()) { case Hexagon::SA1_setin1: MI.insert(MI.begin() + 1, @@ -213,7 +214,6 @@ void adjustDuplex(MCInst &MI, MCContext &Context) { break; } } -} DecodeStatus HexagonDisassembler::getSingleInstruction( MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -551,6 +551,7 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { using namespace Hexagon; + static const MCPhysReg CtrlRegDecoderTable[] = { /* 0 */ SA0, LC0, SA1, LC1, /* 4 */ P3_0, C5, M0, M1, @@ -578,6 +579,7 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { using namespace Hexagon; + static const MCPhysReg CtrlReg64DecoderTable[] = { /* 0 */ C1_0, 0, C3_2, 0, /* 4 */ C5_4, 0, C7_6, 0, @@ -655,5 +657,3 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); return MCDisassembler::Success; } - - |