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| author | quic-akaryaki <123192073+quic-akaryaki@users.noreply.github.com> | 2024-01-18 15:04:32 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-18 15:04:32 -0600 |
| commit | 96542c018f75b54b35aa3e08f184a4909f8c0c04 (patch) | |
| tree | a8a540ac87d54847e916a5961a7a051bb67b18e6 /llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | |
| parent | a9ca820529c69674e01d2e90cadc69e361ecf339 (diff) | |
| download | llvm-96542c018f75b54b35aa3e08f184a4909f8c0c04.zip llvm-96542c018f75b54b35aa3e08f184a4909f8c0c04.tar.gz llvm-96542c018f75b54b35aa3e08f184a4909f8c0c04.tar.bz2 | |
[Hexagon] Flip subreg bit for reverse pairs hvx .new (#75873)
In .new instructions, the upper vector of a reverse pair (e.g. V4 in
V4:5) should be referenced with an odd sss value.
Diffstat (limited to 'llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index c7e22d7..44a5cd7 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -512,6 +512,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB, const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); const unsigned ProdPairIndex = Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0; + if (Rev) + SubregBit = !SubregBit; Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0; } else if (SubregBit) // Hexagon PRM 10.11 New-value operands |