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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-10-22 20:58:35 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-10-22 20:58:35 +0000 |
| commit | 73a51a1a68335849805575bfd23fce6647d07d33 (patch) | |
| tree | 31a7681385b69deac92aaff59290280de7833fd0 /llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | |
| parent | 4f9c0eeff8202dd5afa7953baac4acca9d2355d4 (diff) | |
| download | llvm-73a51a1a68335849805575bfd23fce6647d07d33.zip llvm-73a51a1a68335849805575bfd23fce6647d07d33.tar.gz llvm-73a51a1a68335849805575bfd23fce6647d07d33.tar.bz2 | |
[Hexagon] Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.
http://reviews.llvm.org/D5624
llvm-svn: 220427
Diffstat (limited to 'llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 24dbf2a..b709c83 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -48,6 +48,40 @@ public: };
}
+static const uint16_t IntRegDecoderTable[] = {
+ Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
+ Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
+ Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
+ Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
+ Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
+ Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
+ Hexagon::R30, Hexagon::R31};
+
+static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
+ Hexagon::P2, Hexagon::P3};
+
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t /*Address*/,
+ void const *Decoder) {
+ if (RegNo > 31)
+ return MCDisassembler::Fail;
+
+ unsigned Register = IntRegDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::CreateReg(Register));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
+ uint64_t /*Address*/,
+ void const *Decoder) {
+ if (RegNo > 3)
+ return MCDisassembler::Fail;
+
+ unsigned Register = PredRegDecoderTable[RegNo];
+ Inst.addOperand(MCOperand::CreateReg(Register));
+ return MCDisassembler::Success;
+}
+
#include "HexagonGenDisassemblerTables.inc"
static MCDisassembler *createHexagonDisassembler(Target const &T,
|