diff options
author | Colin LeMahieu <colinl@codeaurora.org> | 2015-02-10 16:59:36 +0000 |
---|---|---|
committer | Colin LeMahieu <colinl@codeaurora.org> | 2015-02-10 16:59:36 +0000 |
commit | 404d5b242de1d849bf048a40a702d2dd04abda10 (patch) | |
tree | 59f46c7ee6a357c561fdb6c96e8998f84b0bdff3 /llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | |
parent | cc8913cc6b4493afa807d19316e83fccc22e607b (diff) | |
download | llvm-404d5b242de1d849bf048a40a702d2dd04abda10.zip llvm-404d5b242de1d849bf048a40a702d2dd04abda10.tar.gz llvm-404d5b242de1d849bf048a40a702d2dd04abda10.tar.bz2 |
[Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class.
llvm-svn: 228708
Diffstat (limited to 'llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 44f9d93..88f633f 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -51,6 +51,8 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, void const *Decoder); static const uint16_t IntRegDecoderTable[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, @@ -105,6 +107,30 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, void const *Decoder) { + static const uint16_t CtrlReg64DecoderTable[] = { + Hexagon::C1_0, Hexagon::NoRegister, + Hexagon::C3_2, Hexagon::NoRegister, + Hexagon::NoRegister, Hexagon::NoRegister, + Hexagon::C7_6, Hexagon::NoRegister, + Hexagon::C9_8, Hexagon::NoRegister, + Hexagon::C11_10, Hexagon::NoRegister, + Hexagon::CS, Hexagon::NoRegister, + Hexagon::UPC, Hexagon::NoRegister + }; + + if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0])) + return MCDisassembler::Fail; + + if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) + return MCDisassembler::Fail; + + unsigned Register = CtrlReg64DecoderTable[RegNo]; + Inst.addOperand(MCOperand::CreateReg(Register)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { unsigned Register = 0; |