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| author | David Green <david.green@arm.com> | 2022-08-08 09:47:55 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2022-08-08 09:47:55 +0100 |
| commit | 061e0189a3dab6b1831a80d489ff1b15ad93aafb (patch) | |
| tree | 57cfe2e0d07fff8821c70434cd5c22bf13147bfd /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | a6dec9f5b2840b77dcf3c1731a68428893501ade (diff) | |
| download | llvm-061e0189a3dab6b1831a80d489ff1b15ad93aafb.zip llvm-061e0189a3dab6b1831a80d489ff1b15ad93aafb.tar.gz llvm-061e0189a3dab6b1831a80d489ff1b15ad93aafb.tar.bz2 | |
[DAG] Ensure Legal BUILD_VECTOR elements types in shuffle->And combine
D129150 added a combine from shuffles to And that creates a BUILD_VECTOR
of constant elements. We need to ensure that the elements are of a legal
type, to prevent asserts during lowering.
Fixes #56970.
Differential Revision: https://reviews.llvm.org/D131350
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions