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author | Mirko BrkuĊĦanin <Mirko.Brkusanin@amd.com> | 2023-12-15 13:45:03 +0100 |
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committer | GitHub <noreply@github.com> | 2023-12-15 13:45:03 +0100 |
commit | 5879162f7fe9be85bbe58776228e79c24bbf2886 (patch) | |
tree | 7899e2d60638be5e4456378e0499c81cb5b0dcec /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | |
parent | f5e48fed043eaa24546aeaa656cb88342d3085e6 (diff) | |
download | llvm-5879162f7fe9be85bbe58776228e79c24bbf2886.zip llvm-5879162f7fe9be85bbe58776228e79c24bbf2886.tar.gz llvm-5879162f7fe9be85bbe58776228e79c24bbf2886.tar.bz2 |
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index eb6ce48..9c85ff3 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -403,11 +403,19 @@ static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact: + case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN: + case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN_exact: + case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET: + case AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET_exact: return BUFFER_LOAD; case AMDGPU::BUFFER_STORE_DWORD_OFFEN: case AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact: case AMDGPU::BUFFER_STORE_DWORD_OFFSET: case AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact: + case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN: + case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact: + case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET: + case AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact: return BUFFER_STORE; } } @@ -429,19 +437,31 @@ static InstClassEnum getInstClass(unsigned Opc, const SIInstrInfo &TII) { switch (AMDGPU::getMTBUFBaseOpcode(Opc)) { default: return UNKNOWN; + case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_exact: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_exact: case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN: case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_exact: case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET: case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_exact: - case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN: - case AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN_exact: - case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN: - case AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN_exact: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN_exact: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN_exact: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN_exact: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET: + case AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET_exact: return TBUFFER_LOAD; case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN: case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact: case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET: case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact: + case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN: + case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact: + case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET: + case AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact: return TBUFFER_STORE; } } |