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| author | Phoebe Wang <phoebe.wang@intel.com> | 2023-12-15 20:41:42 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-15 20:41:42 +0800 |
| commit | f5e48fed043eaa24546aeaa656cb88342d3085e6 (patch) | |
| tree | ead743bb90119629c60779d6ea2f8c3070a4eb8a /llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | |
| parent | 681eacc1b670fd7137d8677fef6fc76c6e37dca9 (diff) | |
| download | llvm-f5e48fed043eaa24546aeaa656cb88342d3085e6.zip llvm-f5e48fed043eaa24546aeaa656cb88342d3085e6.tar.gz llvm-f5e48fed043eaa24546aeaa656cb88342d3085e6.tar.bz2 | |
[X86][AVX10] Allow 64-bit mask register used without EVEX512 (#75571)
This is to reflect new document change that 64-bit mask is support by
AVX10 256-bit targets.
Latest documents can be found in:
https://cdrdv2.intel.com/v1/dl/getContent/784267
https://cdrdv2.intel.com/v1/dl/getContent/784343
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp')
0 files changed, 0 insertions, 0 deletions