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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2023-08-03 09:52:56 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2023-08-21 10:35:58 +0000 |
| commit | 8ce23b8e5c91c530d25c13f97b6f4cbacfe34b3c (patch) | |
| tree | 970d157fe90f5c9c83e102cadfaed8a5e771ca55 /llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | |
| parent | ba818c4019c550e1a413e1563a05b241b508defd (diff) | |
| download | llvm-8ce23b8e5c91c530d25c13f97b6f4cbacfe34b3c.zip llvm-8ce23b8e5c91c530d25c13f97b6f4cbacfe34b3c.tar.gz llvm-8ce23b8e5c91c530d25c13f97b6f4cbacfe34b3c.tar.bz2 | |
[mlir][ArmSME] Add vector to tile intrinsics
Add support for following vector to tile (MOVA) intrinsics to ArmSME
dialect:
llvm.aarch64.sme.write.vert
llvm.aarch64.sme.write.horiz
Includes the definition of new type predicate
'ScalableVectorOfRankAndLengthAndType' in OpBase.td.
Reviewed By: awarzynski, dcaballe
Differential Revision: https://reviews.llvm.org/D157004
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions