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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2023-08-21 11:21:59 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2023-08-21 11:22:07 +0100 |
| commit | ba818c4019c550e1a413e1563a05b241b508defd (patch) | |
| tree | 2f5df8433ec4d49d007e70795e9e670f225366c5 /llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp | |
| parent | 69bd66b3ced6a295b302c6548aba11d7734c2cd7 (diff) | |
| download | llvm-ba818c4019c550e1a413e1563a05b241b508defd.zip llvm-ba818c4019c550e1a413e1563a05b241b508defd.tar.gz llvm-ba818c4019c550e1a413e1563a05b241b508defd.tar.bz2 | |
[DAG] replaceStoreOfInsertLoad - don't fold if the inserted element is implicitly truncated
D152276 wasn't handling the case where the inserted element is implicitly truncated into the vector - resulting in a i1 element (implicitly truncated from i8) overwriting 8 bits instead of 1 bit.
This patch is intended to be merged into 17.x so I've just disallowed any vector element vs inserted element type mismatch - technically we could be more elegant and permit truncated stores (as long as the store is still byte sized), but the use cases for that are so limited I'd prefer to play it safe for now.
Candidate patch for #64655 17.x merge
Differential Revision: https://reviews.llvm.org/D158366
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions