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| author | Tim Northover <Tim.Northover@arm.com> | 2013-02-28 14:46:14 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-02-28 14:46:14 +0000 |
| commit | ce17020c973e7b25aac23405b2a7812f40c1bb5b (patch) | |
| tree | c4f04eb6715761b69c2f24c2d4567ba29f1f14f2 /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
| parent | 9a23be7451ea04fcbcb81ff9df79688bf280addd (diff) | |
| download | llvm-ce17020c973e7b25aac23405b2a7812f40c1bb5b.zip llvm-ce17020c973e7b25aac23405b2a7812f40c1bb5b.tar.gz llvm-ce17020c973e7b25aac23405b2a7812f40c1bb5b.tar.bz2 | |
AArch64: remove post-encoder method from FCMP (immediate) instructions.
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.
llvm-svn: 176261
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index eba7666..12c1b8f 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -106,6 +106,11 @@ static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, + unsigned RmBits, + uint64_t Address, + const void *Decoder); + template<int RegWidth> static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, unsigned FullImm, @@ -381,6 +386,17 @@ static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst, + unsigned RmBits, + uint64_t Address, + const void *Decoder) { + // Any bits are valid in the instruction (they're architecturally ignored), + // but a code generator should insert 0. + Inst.addOperand(MCOperand::CreateImm(0)); + return MCDisassembler::Success; +} + + template<int RegWidth> static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst, |