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| author | Hao Liu <Hao.Liu@arm.com> | 2013-10-10 14:59:36 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2013-10-10 14:59:36 +0000 |
| commit | c319193636480a19a0faf757b851b53d155e7ccd (patch) | |
| tree | 409623443b48225ea63aa27ce071c51b5b06e813 /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
| parent | b3b79a434580f28a2e44dac70e3f6f5e88e98f79 (diff) | |
| download | llvm-c319193636480a19a0faf757b851b53d155e7ccd.zip llvm-c319193636480a19a0faf757b851b53d155e7ccd.tar.gz llvm-c319193636480a19a0faf757b851b53d155e7ccd.tar.bz2 | |
Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).
E.g. ld1(3 registers version) will load 32-bit elements {A, B, C, D, E, F} sequentially into the three 64-bit vectors list {BA, DC, FE}.
E.g. ld3 will load 32-bit elements {A, B, C, D, E, F} into the three 64-bit vectors list {DA, EB, FC}.
llvm-svn: 192351
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions