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| author | David Sherwood <david.sherwood@arm.com> | 2022-10-26 10:40:02 +0000 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2022-11-02 08:39:03 +0000 |
| commit | be369ea31b98f23c7d8e7a83ea4a1b4cf76b544f (patch) | |
| tree | 5369e96bb9014d14aa7f62a9d4a649885183aaba /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
| parent | 870fbf8e300f3012470593ac087219a04d52857f (diff) | |
| download | llvm-be369ea31b98f23c7d8e7a83ea4a1b4cf76b544f.zip llvm-be369ea31b98f23c7d8e7a83ea4a1b4cf76b544f.tar.gz llvm-be369ea31b98f23c7d8e7a83ea4a1b4cf76b544f.tar.bz2 | |
[AArch64][SVE2] Add the SVE2.1 while & pext predicate pair instructions
This patch adds the assembly/disassembly for the following
predicate pair instructions:
pext: Set pair of predicates from predicate-as-counter
whilelt: While incrementing signed scalar less than scalar
whilele: While incrementing signed scalar less than or equal to scalar
whilegt: While incrementing signed scalar greater than scalar
whilege: While incrementing signed scalar greater than or equal to scalar
whilelo: While incrementing unsigned scalar lower than scalar
whilels: While incrementing unsigned scalar lower or same as scalar
whilehs: While decrementing unsigned scalar higher or same as scalar
whilehi: While decrementing unsigned scalar higher than scalar
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136759
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index b5f205f7..1438f02 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -140,6 +140,12 @@ static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder); +static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, uint64_t Address, @@ -707,6 +713,29 @@ DecodePPR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, return DecodePPRRegisterClass(Inst, RegNo + 8, Addr, Decoder); } +static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 15) + return Fail; + + unsigned Register = + AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo); + Inst.addOperand(MCOperand::createReg(Register)); + return Success; +} + +static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if ((RegNo * 2) > 14) + return Fail; + unsigned Register = + AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2); + Inst.addOperand(MCOperand::createReg(Register)); + return Success; +} + static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder) { |