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author | Spencer Abson <Spencer.Abson@arm.com> | 2024-10-21 15:47:10 +0000 |
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committer | Spencer Abson <Spencer.Abson@arm.com> | 2024-10-21 16:11:58 +0000 |
commit | 42ba452aa94e4da277842d8990ad958a6256e558 (patch) | |
tree | 4ae24ea80fbcad15425e7ab45d3a9f9d0c777507 /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
parent | 8417f6af54c8f6dcf5893ab1352b50bf33c5a1ba (diff) | |
download | llvm-42ba452aa94e4da277842d8990ad958a6256e558.zip llvm-42ba452aa94e4da277842d8990ad958a6256e558.tar.gz llvm-42ba452aa94e4da277842d8990ad958a6256e558.tar.bz2 |
[NFC] Fix -WError for unused Encode/Decode ZK methods
Remove the unused functions and register classes from the change below
https://github.com/llvm/llvm-project/commit/4679583181a9032b4f7c6476c7a1bfefe5724b47
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 4a4b89d..87c4245 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -49,8 +49,6 @@ template <unsigned Min, unsigned Max> static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, - const MCDisassembler *Decoder); template <unsigned Min, unsigned Max> static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -389,22 +387,6 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo, return Success; } -// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in -// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011 and Z28-Z31 = 100, 101, 110, -// 111 -static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address, - const MCDisassembler *Decoder) { - // RegNo < 4 => Reg is in Z20-Z23 (offset 20) - // RegNo >= 4 => Reg is in Z28-Z31 (offset 24) - unsigned Reg = (RegNo < 4) ? (RegNo + 20) : (RegNo + 24); - if (!(Reg >= 20 && Reg <= 23) && !(Reg >= 28 && Reg <= 31)) - return Fail; - unsigned Register = - AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg); - Inst.addOperand(MCOperand::createReg(Register)); - return Success; -} - static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { |