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author | Sergei Barannikov <barannikov88@gmail.com> | 2025-09-05 15:42:59 +0300 |
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committer | GitHub <noreply@github.com> | 2025-09-05 12:42:59 +0000 |
commit | 25498dfef000f906ad4287d09c4e036a27552cb6 (patch) | |
tree | 70d51bb081b697cbe4041d4a93da652425bf6b3a /llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | |
parent | e031a56a1834aed848e5a940aeb074fc2b1cbc63 (diff) | |
download | llvm-25498dfef000f906ad4287d09c4e036a27552cb6.zip llvm-25498dfef000f906ad4287d09c4e036a27552cb6.tar.gz llvm-25498dfef000f906ad4287d09c4e036a27552cb6.tar.bz2 |
[AArch64] Provide a custom decoder for LDR_ZA/STR_ZA (#156363)
These instructions encode two operands in the same field. Instead of
fixing them after they have been incorrectly decoded, provide a custom
decoder.
This will allow to remove `-ignore-non-decodable-operands` option from
AArch64/CMakeLists.txt, see #156358 for the context.
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
-rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 23e46b8..8c1e9f6 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1563,6 +1563,25 @@ static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn, return Success; } +static DecodeStatus +DecodeSMESpillFillInstruction(MCInst &Inst, uint32_t Bits, uint64_t Addr, + const MCDisassembler *Decoder) { + unsigned RvBits = fieldFromInstruction(Bits, 13, 2); + unsigned RnBits = fieldFromInstruction(Bits, 5, 5); + unsigned Imm4Bits = fieldFromInstruction(Bits, 0, 4); + + DecodeSimpleRegisterClass<AArch64::MatrixIndexGPR32_12_15RegClassID, 0, 4>( + Inst, RvBits, Addr, Decoder); + Inst.addOperand(MCOperand::createImm(Imm4Bits)); + DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, RnBits, + Addr, Decoder); + // Spill and fill instructions have a single immediate used for both + // the vector select offset and optional memory offset. Replicate + // the decoded immediate. + Inst.addOperand(MCOperand::createImm(Imm4Bits)); + return Success; +} + #include "AArch64GenDisassemblerTables.inc" #include "AArch64GenInstrInfo.inc" @@ -1621,16 +1640,6 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, } } - if (MI.getOpcode() == AArch64::LDR_ZA || - MI.getOpcode() == AArch64::STR_ZA) { - // Spill and fill instructions have a single immediate used for both - // the vector select offset and optional memory offset. Replicate - // the decoded immediate. - const MCOperand &Imm4Op = MI.getOperand(2); - assert(Imm4Op.isImm() && "Unexpected operand type!"); - MI.addOperand(Imm4Op); - } - if (Result != MCDisassembler::Fail) return Result; } |