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| author | Charitha Saumya <136391709+charithaintc@users.noreply.github.com> | 2025-02-24 13:50:06 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-02-24 22:50:06 +0100 |
| commit | e5ce0304335dc1cae6856c880d1d4e14dcf8265d (patch) | |
| tree | b1cd459b453f15b1242fbd2d00fa104abe589154 /llvm/lib/ExecutionEngine/Orc/ThreadSafeModule.cpp | |
| parent | eabe2eb933556bf3e0db0d2d98e96f962bde14dc (diff) | |
| download | llvm-e5ce0304335dc1cae6856c880d1d4e14dcf8265d.zip llvm-e5ce0304335dc1cae6856c880d1d4e14dcf8265d.tar.gz llvm-e5ce0304335dc1cae6856c880d1d4e14dcf8265d.tar.bz2 | |
[mlir][xegpu] Improve XeGPU op verification logic for SIMT flavor and update tests. (#127920)
This PR adds required changes for XeGPU ops to support the SIMT
distribution.
1. Adds verification logic for SIMT flavor for load_nd, store_nd, dpas,
load_gather and store_scatter ops.
2. Adds test cases to cover the SIMT version of these ops along with
their VC counter parts.
---------
Co-authored-by: Artem Kroviakov <71938912+akroviakov@users.noreply.github.com>
Diffstat (limited to 'llvm/lib/ExecutionEngine/Orc/ThreadSafeModule.cpp')
0 files changed, 0 insertions, 0 deletions